STG-Based Resynthesis for Balsa Circuits

Stanislavs Golubcovs, Walter Vogler, Norman Kluge

in: Augsburg Technical Report, Institute of Computer Science, University of Augsburg, November 2013

Balsa provides a rapid development flow, where asynchronous circuits are created from high-level specifications, but the syntax-driven translation used by the Balsa compiler often results in performance overhead. To reduce this performance penalty, various control resynthesis and peephole optimization techniques are used; in this paper, STG-based resynthesis is considered. For this, we have translated the control parts of almost \emph{all }components used by the Balsa compiler into STGs; in particular we separated the control path and the data path in the data components. A Balsa specification corresponds to the parallel composition of such STGs, but this composition must be reduced. We have developed new reduction operations and, using real-life examples, studied various strategies how to apply them.