Safety-Critical TM on Intel CPUs

Safety-Critical Transactional Memory on Intel CPUs

Start date: 01.01.2013
Funded by: Intel Germany Microprocessors Lab Research Grant on High-Performance Computing in Safety Critical Systems
Local head of project: Prof. Dr. Theo Ungerer
Local scientists: Dr. Sebastian Weis
Florian Haas
External scientists / cooperations: Gilles Pokam, Software and Systems Research, Intel, Santa Clara
Youfeng Wu, Programming Systems Lab, Intel, Santa Clara
Publications: Publication list


Future safety-critical applications in automotive systems, will require a much higher performance than automotive applications of today. Nevertheless, these applications underlie the same timing constraints and fault-tolerance requirements as common safety-critical applications. Current embedded processors cannot provide the necessary performance for such applications. Therefore, it is promising to use COTS (Commercial Off-The-Shelf) multi-/many-core processors, which can deliver the demanded computational power. However, COTS architectures lack the support for fault-tolerance and timing predictability that safety-critical applications require. Thus, novel approaches have to be developed leveraging the given features and characteristics of COTS multi-/many-core processors.

This project focuses on the exploitation of transactional memory (TM) for the execution of parallel safety-critical applications. The objective is to explore the usability of hardware transactional memory (HTM) for safety-critical applications by controlling the task interferences in parallel mixed-criticality applications and leveraging TM as mechanism for recovery and fault containment. Finally both aspects will be combined towards a fault-tolerant execution of parallel safety-critical applications. The core of our approach is a combined software-/hardware-based solution, which exploits given hardware features of future multi-/many-core processors to guarantee a reliable and timely execution of parallel safety-critical applications.