Start date: 01.01.2010
End date: 31.03.2014
Funded by: EC (European Community)
Local head of project: Prof. Dr. Theo Ungerer
Local scientists: Sebastian Weis
External scientists / cooperations: Roberto Giorgi (Project Leader), Sandro Bartolini (University of Siena)
Mateo Valero, Nacho Navarro, Yoav Etsion (Barcelona Supercomputing Center, Spain)
Francois Bodin (CAPS entreprise, France)
Paolo Faraboschi, Eduardo Argollo (Hewlett-Packard Labs Barcelona, Spain)
Albert Cohen (INRIA, France)
Avi Mendelson (Microsoft R&D Israel)
Eric Lenormand, Philippe Bonnot, Teodora Petrisor (THALES)
Paraskevas Evripidou, Pedro Trancoso (University of Cyprus)
Publications: Publication list


Parallel systems will in future be widely available in form of multi-/many-core building blocks with hundreds or thousands of cores on a chip.

In order to address the programmability challenges of such many-cores, we combine an underlying dataflow-based thread execution with advanced programming models like transactional memory.

The second challenge addressed by this project is the definition of an appropriate architecture to match the proposed execution model and reliability challenges. The architectural explorations will cover the concepts of data-driven and decoupled thread execution, provide architectural support for the parallel programming model, introduce specific hardware scheduling units able to manage different levels of thread granularities, take care of code or data migration based on information passed by the virtual layer, and consider power, thermal, and fault information. The underlying architectural elements will essentially encompass a heterogeneous architecture trying to reuse existing ”off-the-shelf” or well-known components.

The third challenge, which is the particular objective of University of Augsburg, concerns reliability issues: such a large number of cores together with the high density of the components that are integrated into the chip results obviously in systems that will suffer from failures during runtime. These failures may be transient or permanent. The system must provide mechanisms to detect such failures and resume execution with reconfigured core, link and memory assignments in order to complete the execution successfully.

Our approach for evaluating the research proposals is based on a many-core simulator model provided by the COTSon simulation framework of TERAFLUX partner HP Labs.

Partners in the TERAFLUX project are the University of Siena, the Barcelona Supercomputing Center, CAPS Enterprise, Hewlett Packard, INRIA, Microsoft, THALES, the University of Cyprus, the University of Manchester, and the Chair of Systems and Networking of the University of Augsburg.