|Funded by:||DFG (Deutsche Forschungsgemeinschaft)|
|Local project leader:||Prof. Dr. Theo Ungerer|
|External scientists / cooperations:||
Uwe Brinkschulte (University of Karlsruhe, Department of Computer Science)
Rafael Zalman (Infineon Technologies AG)
HiPEAC Cluster "Investigation of real-time capable embedded SMT processor techniques"
CAR-SoC defines a new SoC approach that emphasizes Connectivity, Autonomic computing principles, and Real-time requirements on a chip. The requirements shall be fulfilled by a multithreaded processor core in combination with a reconfigurable architecture. The multithreaded processor core is based on Infineon's TriCore architecture extended by an integrated powerful real-time scheduling. Helper threads running with low priority in own thread slots concurrent to the application implement autonomic managers that monitor relevant on-chip characteristics like processor workload and memory usage. The autonomic managers decide in combination with a middleware if self-optimization, self-configuration, self-protection, or self-healing techniques must be triggered.
The following figure presents the CAR-SoC system architecture. Several CAR-SoC nodes can be connected by a real-time middleware transparent to the application. Two closed-control-loops are responsible for the autonomic/organic management: one on the local node level and the other on the middleware level.
The processor core is based on the architecture of Infineon's TriCore processor. It is extended by the ability of simultaneous multithreading. An internal real-time scheduler should fulfill the hard real-time requirements of a number of threads. The hardware scheduler hides the boundaries of software and hardware threads. It selects several threads out of the systems thread list which will be executed within the multithreaded pipeline. Thread swapping is done automatically without software support, i.e. without software overhead. A powerful scheduling scheme enables thread scheduling similar to the Guaranteed Percentage (GP) scheduling (see Komodo project) in combination with the Least Laxity First (LLF) scheduling.
A HiPEAC funded cooperation of the Universities of Augsburg and Delft explores the potentials and problems when combining a multithreaded processor core with reconfigurable hardware within an embedded SoC. The cooperation already resulted in an interface design and System-C implementation that combines the simultaneous multithreaded CAR-SoC processor (called CAR-Core) developed at University of Augsburg with the reconfiguration unit of the MOLEN processor developed at University of Delft. Simulations showed a three-fold speedup on an MJPEG application over the pure software-based execution.
Because the CAR-SoC is designed for embedded and ubiquitous systems, an extremely small software kernel is required. We just implement a new system architecture following the mirco-kernel proncipals. The kernel is only responsible for memory and thread management, i.e. thread creation, termination and synchronization. Scheduling is done by the CarCore processor. Additionally, the system kernel is able to link together several libraries and applications. One of these libraries/applications will be the CAR-SoC middleware, which will offer more powerful system functions.
Due to the efficient scheduling, the coexistence of hard-real-time, soft-real-time and non-real-time threads is possible. We will implement several soft- and non-real-time threads which will monitor miscellaneous system parameters. Additionally, so-called Autonomic Managers will analyze the system parameters and if necessary trigger some suitable retaliatory actions to realize the self-X properties.