*) VIONA Development GmbH, Karlstr. 27, D-76133 Karlsruhe, uli@viona.de
We survey microarchitecture models for a general-purpose processor with multimedia enhancements. Such enhancements are provided by one or more multimedia units that employ subword parallelism (data parallel "SIMD" instructions), saturation arithmetic and additional arithmetic, masking, selection, reordering and conversion instructions.
A multithreaded processor, in general, stores multiple thread contexts in different register sets on the processor chip and multiplexes the functional units between the contexts. Context switching is very fast. Thereby all kinds of latencies can be bridged by switching to another thread. A simultaneous multithreaded processor, in particular, can issue instructions from several threads simultaneously.
We start with a wide-issue superscalar processor model, enhance it by multimedia units, by the simultaneous multithreading technique, and by an additional on-chip RAM storage. Our workload is a multithreaded MPEG-2 video decompression algorithm that extensively uses multimedia units.
The simulations showed that a single-threaded, 8-issue maximum processor (assuming an abundance of resources) reaches an IPC (instructions per cycle) count of only 1.60, while an 8-threaded 8-issue processor is able to reach an IPC of 6.07. A more realistic processor model reaches an IPC of 1.27 in the single-threaded 8-issue vs. 3.21 in the 8-threaded 8-issue model. So, the generalizing conclusion is that an 8-threaded 8-issue processor may yield up to threefold performance increase over the single-threaded 8-issue model. A supplementary tool allows us to estimate the transistor count and chip space of the simulated models.
Ulrich
Sigmund, Marc Steinhaus, Theo Ungerer: On Performance, Transistor Count and Chip
Space Assessment of Multimedia-enhanced Simultaneous Multithreaded Processors.
Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC-4),
Monterrey, Ca., Dec. 10, 2000 (in postscript,
in pdf).
U. Sigmund, Th. Ungerer: Die Multimediafähigkeit von mehrfädig superskalaren Prozessoren am Beispiel der MPEG-2-Decodierung. To be published in the Journal: Informatik Forschung und Entwicklung, 2000 (in German)
U. Sigmund, Th. Ungerer: Parallelisierbarkeit von Multimediaanwendungen für mehrfädig superskalare Prozessoren am Beispiel der MPEG-2-Dekodierung. Journal: it+ti, No. 5, October 2000, 22-32 (in German).
U. Sigmund: Entwurf und Evaluierung mehrfädig superskalarer Prozessortechniken im Hinblick auf Multimedia. PhD Thesis (Doctoral Dissertation), University of Karlsruhe, May 2000 (in German, on-line access).
H. Oehring, U. Sigmund, Th. Ungerer: Performance of Simultaneous Multithreaded Multimedia-enhanced Processors for MPEG-2 Video Decompression. Journal of Systems Architecture, Vol. 46, No. 11, 2000, 1033-1046.
U. Sigmund, Th. Ungerer: Latency and Bandwidth Considerations for MPEG-2 Video Decompression on Simultaneous Multithreaded Processors. Proceedings: The 2000 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA‘2000), Las Vegas, June 26-29, 2000.
U. Sigmund, T. Ungerer: Memory Hierarchy Studies of Multimedia-enhanced Simultaneous Multithreaded Processors for MPEC-2 Video Decompression. Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC 00), Toulouse, Jan. 8., 2000 (in postscript, in pdf).
H. Oehring, U. Sigmund, Th. Ungerer: MPEG-2 Video Decompression on Simultaneous Multithreaded Multimedia Processors. 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT '99), Newport Beach, Ca., Oct. 12-16, 1999, pp. 11-16 (in postscript, in pdf).
H. Oehring, U. Sigmund, Th. Ungerer: Simultaneous Multithreading and Multimedia. Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC 99) in conjunction with Fifth International Symposium on High Performance Computer Architecture (HPCA-5), Orlando, Jan. 9-12, 1999 (in postscript, in pdf).
H. Oehring, U. Sigmund, Th. Ungerer: Evaluierung mehrfädiger Prozessortechniken zur Weiterentwicklung von Multimediaprozessoren. 15. GI/ITG-Fachtagung ARCS’99 Architektur von Rechensystemen 1999, Jena 4.-7.10.1999, pp. 83-90 (in German).
Th. Ungerer: Multimedia and Simultaneous Multithreading. Abstract. Dagstuhl Seminar 98351: Architectural and Arithmetic Support for Multimedia. August 31 - September 9, 1998.
H. Oehring: Evaluierung von Konzepten zur Weiterentwicklung von Multimediaprozessoren. Diplomarbeit. Fakultät für Informatik. Universität Karlsruhe 1998.
To Ungerer's
homepage.
Theo Ungerer, April
2006