The primary intended audience of this book are computer and/or electrical engineers and researchers in the fields of computer science. It can also be used as a textbook for processor architecture or advanced microprocessor courses at the graduate student level of computer science or electrical engineering.A comprehensive collection of lecture slides covering all tutorial parts of the book is available in PowerPoint (Office 2000), PDF, and Postscript: A sample reading of the preface introduces all chapters of the book (in pdf, in Postscript).The book surveys architectural mechanisms and implementation techniques for exploiting fine-grained and coarse-grained parallelism within microprocessors. It starts with a review of the basic instruction set architecture and pipelining techniques, continues with a comprehensive account of state-of-the-art superscalar and VLIW techniques used in microprocessors. It covers both the concepts involved and implementations in modern microprocessors. The book ends with a thorough review of the research techniques that will lead to future microprocessors.
The table of contents (in pdf, in Postscript).
Customer Comments of Amazon.comThe home pages of the authors are
Average Customer Review: 5 stars
An excellent review of processor architectures
Reviewer: James (jamesl4242@aol.com) from Connecticut
October 17, 1999This monograph does a fine job of reviewing the past, present, and emerging
future of processor architectures in a a very approachable way. Even those who
are not engineers, nor particularly familiar with the innerworkings of computers
should be able to get a lot of information out of this book, and come away with a
better understanding of the systems they interact with daily. A very enjoyable
read, and will bring even those more familiar with its material up to speed on
architectures past and present.source: http://www.amazon.com/exec/obidos/ASIN/3540647988/qid%3D943630239/103-8714018-6578224
Jurij Silc at Jozef Stefan
Institute, Ljubljana, Slovenia.
Borut Robic at
University of Ljubljana, Slovenia, and
Theo Ungerer
at University of Augsburg, Germany.
General Springer-Verlag home page.
Book's
homepage at Springer-Verlag.
For corrections, suggestions and improvements please send Email to Theo Ungerer or contact personally.
The CPU Info Center of the University of California, Berkeley, at http://bwrc.eecs.berkeley.edu/CIC/ collects information on commercial microprocessors such as, e.g., CPU announcements, on-line technical documentations, a die photo gallery, and much more.
An excellent guide to resources on high-performance microprocessors is the "VLSI microprocessor" home page www.microprocessor.sscc.ru at the Supercomputer Software Department RAS.
The National Technology Roadmap for Semiconductors at http://www.sematech.org/public/home.htm is a description of the semiconductor technology requirements for ensuring advancements in the performance of integrated circuits. Sponsored by the mSemiconductor Industry Association (SIA) and published by SEMATECH, this mreport is the result of a collaborative effort between industry manufacturers mand suppliers, government organizations, consortia, and universities.
The newest commercial microprocessors are presented at the Microprocessor Forum, the Hot Chips Conference, and the International Solid State Circuit Conference (ISSCC).
The most important conferences on research in processor marchitecture are the Annual International Symposium on Computer Architecture m(ISCA), the biennial International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), the International Symposium on High-Performance Computer Architecture (HPCA), the Annual International Symposium on Microarchitecture (MICRO), and the Parallel Architectures and Compilation Techniques (PACT) conference.
Last changes Aug 22, 2002 by Theo Ungerer (ungerer@informatik.uni-augsburg.de)