Multi-Core Execution of Hard Real-Time Applications Supporting Analysability
|Funded by:||EU (Europäische Union)|
|Local project leader:||Prof. Dr. Theo Ungerer|
|External scientists / cooperations:||
Mateo Valero, Francisco J. Cazorla, Eduardo Quinones, Marco Paolieri (Barcelona Supercomputer Center, Spanien)
Pascal Sainrat, Christine Rochange, Hugues Cassé (Université Paul Sabatier, Toulouse, France)
Zlatko Petrov, Frantisek Mikulu, Lukas Kellner (Honeywell, Prag und Brno, Czech Republic)
Guillem Bernat, Antoine Colin, Michael Houston (Rapita Systems Ltd., UK)
Providing higher performance than what state-of-the-art embedded processors can deliver today will increase safety, comfort, number and quality of services, lower emissions and fuel demands of automotive, aerospace, space, and construction machinery applications. Multi-core processors are increasingly being considered as the solution to achieve an increased processor performance, while maintaining low chip costs and low power consumption. However, current trends in mainstream multi-core processor design result in processors with certainly reduced average execution times, but typically with unpredictable and unanalysable (or extremely pessimistic) worst case behaviour that deems them unusable in the domain of safety-related real-time embedded systems.
The MERASA project will develop multi-core processor designs (from 2 to 16 cores) for hard real-time embedded systems hand in hand with timing analysis techniques and tools to guarantee the analysability and predictability regarding timing of every single feature provided by the processor. Design exploration activities will be performed in conjunction with the timing analysis tools. The project will address both static WCET analysis tools (the OTAWA toolset) as well as hybrid measurement-based tools (RapiTime) and their interoperability. It will also develop system-level software with predictable timing performance.
To constrain production costs and technology integration risks, we investigate hardware-based real-time scheduling solutions that empower the same multi-core processor to handle hard, soft, and non real-time tasks on different cores. The developed hardware/software techniques will be evaluated by application studies from aerospace, automotive, and construction-machinery areas performed by selected industrial partners.