Publications

Transistor Count and Chip-Space Estimation of SimpleScalar-based Microprocessor Models
Steinhaus Marc, Kolla Reiner, Larriba-Pey Josep L., Ungerer Theo, Valero Mateo
Workshop on Complexity-Effective Design, June 30, 2001, in conjunction with the 28th International Symposium on Computer Architecture June 30 - July 4, 2001, Göteborg, Sweden
Transistor Count and Chip-Space Estimation of Simulated Microprocessors
M. Steinhaus, R. Kolla, J. L. Larriba-Pey, Th. Ungerer, M. Valero
Submitted for publication, available as Research report UPC-DAC-2001-16, UPC, Barcelona, Spain

On Performance, Transistor Count and Chip Space Assessment of Multimedia-enhanced Simultaneous Multithreaded Processors
Ulrich Sigmund, Marc Steinhaus, Theo Ungerer
Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC-4), Monterrey, Ca., Dec. 10, 2000