Publikationen bis 2011

2011

B. Fechner:      3,14159... oder die näherungsweise Berechnung von π, Informatik-Spektrum,
vol. 5/10, ISSN: 0170-6012, Springer-Verlag

B. Fechner:   Reliability Bottlenecks in Integrated Parallel Fault-Tolerant Systems. In Proc. 7^th ARCS/VERFE Workshop, GI

B. Fechner:   Reliability Bottlenecks in Integrated Parallel Fault-Tolerant Systems.

              Angenommen: Journal of Concurrency and Computation: Practice & Experience, Wiley,
                         ISSN 1532-0626

2010

B. Fechner:     GPU-Based Parallel Signature Scanning and Hash Generation.

                   In Proc. 6^th ARCS/ PARS Workshop, GI                       

B. Fechner:     Analysis and Cure of Timing Master Faults.
                        Elektronik automotive, S2/März 2010
                        Sonderausgabe MOST

B. Fechner, O. Körber:
                         Improving the Robustness of a Body-Gesture Control.

                          In Proc. 5^th Int’l. Conf. on Dependability of Computer Systems

B. Fechner:     Not Yet another Language for Petri Nets.
                        In Proc. 19^th European Conf. on Safety and Reliability
B. Fechner:     A Fault Model for Integrated Parallel Systems.
                         In Proc. 19^th European Conf. on Safety and Reliability

2009

B. Fechner, J. Keller:

                            Efficient Fault-Tolerant Addition by Operand Width Consideration.

                            In Proc. 6^th ARCS/ Workshop on Dependability and Fault-Tolerance, GI

S. Einer, B. Fechner, J. Keller:

                            Petri Net Analysis of Non-Redundant and Redundant Execution Schemes.

                            In Proc. 6^th ARCS/ Workshop on Dependability and Fault-Tolerance, GI

B. Fechner:     Rollback and Roll-forward of Architecturally Fixed and Non-Fixed States.
                            In Proc. 18^th European Conf. on Safety and Reliability

K. Echtle, B. Fechner, J. Keller:

                               PAMOS and PAROS - Parallel Addition of Multiple or Redundant Operands in a Single Word.

                               In Proc. 18^th European Conf. on Safety and Reliability

B. Fechner:     Fault-Masking Capabilities of Basic Circuit Structures.

                               In Proc. 4^th Int’l. Conf. on Dependability of Computer Systems

O. Körber, B. Fechner:

                               Remote HID Control of Presentations.

                               In Proc. 5^th Int'l. Conf. on Multimedia and Information and
                      Communication Technologies in Education

B. Fechner, A. Osterloh:

                               A Metalevel True Random Number Generator.

                               Int’l. Journal of Critical Computer Based Systems, Inderscience,

                               ISSN 1757-8779

2008

B. Fechner, U. Hönig, J. Keller, W. Schiffmann:

                               Fault-Tolerant Static Scheduling for Grids.

                               In Proc. 22^nd Int’l. Symp. on Parallel and Distributed Processing

B. Fechner, A. Osterloh:

                               A True Random Number Generator with Built-in Attack Detection.

                               In Proc. 3^rd Int’l. Conf. on Dependability of Computer Systems

B. Fechner:    A Dynamic Fault Classification Scheme.

                               In Proc. 17^th European Conf. on Safety and Reliability

2007

B. Fechner:     A Fault-Tolerant Dynamic Fetch Policy for
                 Multithreaded Processors in Multi-Bus Environments.
                  In Proc. 5^th Int’l. Symp. on Parallel Computing in Electrical Engineering

B. Fechner, L. Beyer, J. Keller:
                        Analysis of Software-Based Recovery Schemes for SMT Processors.

                   In Proc.Int’l. Conf. on Parallel and Distributed Computing and Systems

B. Fechner, J. Keller:
                         Compression-free Checksum-based Fault-Detection Schemes for Pipelined Processors.
                         In Proc. ARCS/ Workshop on Reliability and Fault-Tolerance, GI
B. Fechner, A. Osterloh:
                         Transient Fault Detection in State-Automata.
                          In Proc. 2^nd Int’l. Conf. on Dependability of Computer Systems

2006

B. Fechner:    Microcode with Embedded Timing Constraints.
                               In Proc. ARCS/ Workshop on Dependability and Fault Tolerance, GI
B. Fechner, J. Keller, A. Wohlfeld:
                               Web Server Protection by Customized Instruction Set Encoding.
                               In Proc. 20th Int’l. Symp. on Parallel and Distributed Processing
B. Fechner:    Analysis of Checksum-Based Execution Schemes for Pipelined Processors.
                               In Proc. 20th Int’l. Symp. on Parallel and Distributed Processing
B. Fechner:    A Result Propagation Scheme for Redundant Multithreaded Systems.
                               In Proc. 2006 Int’l. Conf. on Parallel and Distributed Processing Techniques and Applications

2005

B. Fechner:    Dynamic delay-fault injection for reconfigurable hardware.
                               In Proc. 19^th Int’l. Symp. on Parallel and Distributed Processing

B. Fechner, J. Keller, P. Sobe:
                               Classification and Unified Modeling for Duplication-based Recovery.
                               In Proc. 5^th European Dependable Computing Conference

B. Fechner:    Securing Execution in Simultaneous Multithreaded Processors.
                               In Proc. 5^th European Dependable Computing Conference

2004

B. Fechner, J. Keller, P. Sobe:
                               Virtual Duplex Systems with Forward Error Correction on
                               Simultaneous Multithreaded Processors.
                               In Proc. 18^th Int’l. Symp. on Parallel and Distributed Processing

B. Fechner, J. Keller:
                               A Fault-Tolerant Voting Scheme for Multithreaded Environments.
                               In Proc. 4^th Int’l. Symp. on Parallel Computing in Electrical Engineering